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Stripping WAV (RIFF) files

I've been organizing my music recently, and I ran into a couple of old WAV format MP3s. Not all software can deal with WAVs, and since MP3 files are simply the raw MPEG-Layer 3 audio stream, I decided to make a simple program that extracts the audio data from a WAV (RIFF) file.

A WAV file is basically an RIFF, like an RIFF file it consist of multiple tagged blocks, called chunks, that start with a four letter (ASCII) "ID" (tag) and a 32 bit chunk length field. Later versions of WAV have additional information and a feature to record more than 4GB of data per file, but those features are irrelevant for my goals. The basic WAV file consists single RIFF chunck that has an "fmt" chunk and a "data" chunk. The data chunk contains the actual audio data, and is all I'm interested in. The program scans the chunks in the file until it finds the "data" chunk, then it copies the information in the data chunk to a new file.

The source code for this program can be downloaded from the downloads section, it's a microsoft Visual Studio 2010 project.

ECC enabled?

Recently I ordered a new workstation from Alternate to replace my (slightly) aging Core 2 Duo based system. After the positive experience with my Xeon E3 based Dell PowerEdge T110-II I decided to get another Xeon E3 based machine. I chose an Asus P8C-WS motherboard, which is based on the Intel C216 chipset. This chipset supports USB 3.0, SATA 6 Gbps and ECC memory. For extra reliability I got 16 GiB of Kingston ECC memory. On first boot I immediately noticed that the BIOS Setup didn't have an option to enable ECC, nor was it showing whether ECC is enabled. After updating the BIOS to the latest version an ECC option became available, but it can only be set to "automatic" and "disabled".

Not trusting "automatic", it still wasn't clear whether ECC really is enabled. I then decided to check the Intel datasheet for the 3rd generation Core processor to identify the register that controls the ECC functionality. It turns out there are two registers controlling this, one for each memory channel. I then programmed a simple Linux C program to read these registers (directly via /dev/mem). It turns out the ECC functionality is enabled on my system when set to "automatic" in the BIOS setup.

The source code for the tool is available in the downloads section of this website. You can compile it with:

gcc -Wall c2xx_memory_status.c -o c2xx_memory_status

You can then run it as root, the output should look something like this:

Intel C2xx memory status

Channel 0
-------------------------------------------------------------------------------
Size of DIMM A:            4096 MiB
Size of DIMM B:            4096 MiB
DIMM A DDR width:          X8 chips
DIMM B DDR width:          X8 chips
DIMM A number of ranks:    Dual rank
DIMM B number of ranks:    Dual rank
DIMM A select:             DIMM 0
Enhanched Interleave Mode: On
Rank Interleave:           On
ECC:                       On
Error status:              No ECC errors detected

Channel 1
-------------------------------------------------------------------------------
Size of DIMM A:            4096 MiB
Size of DIMM B:            4096 MiB
DIMM A DDR width:          X8 chips
DIMM B DDR width:          X8 chips
DIMM A number of ranks:    Dual rank
DIMM B number of ranks:    Dual rank
DIMM A select:             DIMM 0
Enhanched Interleave Mode: On
Rank Interleave:           On
ECC:                       On
Error status:              No ECC errors detected